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Altera_Forum
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15 years ago

Dual Port RAM Init

Hi, I have generated a DPRAM with the Megawizard, and I have used it in my design. When I have simulated it into Modelsim, all was ok. But when I have compiled my FPGA with my design, there w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

What are the memory related files that you use for synthesis? I had initialization problem in Qsys in simulation. I solved it by modifying the path of the `include in the <memory_name>.v file.