New ContributorI am interested in the DK-DEV-5CSXC6N-B development kit. Could someone contact us to discuss technical details regarding hardware, firmware, and software? We are developing a product for aviation applications.
Frequent ContributorHi Jonel,
Sorry for the delay as I just got back to office last week, still checking on the case. Will get back to you.
Thanks
Regards
Kian
Frequent ContributorHi Jonel,
Sorry for the delay, was wondering anyone contacted you as I forwarded your queries to our NA sales/sales tech team as I did not get any reply back from them and we also had a few public holidays on our end.
Anyway for your questions
Our FPGA code for Ethernet is connected to the HPS with an HPS wrapper, whereas in the Intel Eval Kit, the Tri-Speed MAC soft core is used. Is there any advantage to using the Tri-Speed MAC in this case?
Support wise, we have reference design example coverage for Tri Speed MAC and also user guide for it. Tri Speed MAC is also easier to achieve the rated speed .
2. We have identified a possible cause of the issue—using ethtool, we observed that the link is running at 10 Mbps half-duplex, even though we intended it to be 100 Mbps full-duplex.
Did you try forcing to 100Mbps using ethtool (eg. ethtool -s eth0 speed 100 duplex full autoneg off to force to 100Mbps to see whether that is achievable) , and could you provide the ethtool report.
Some possible causes: Assuming no issues with the ethernet cable, is the auto negotiating enabled, or any issues with it as when auto negotiating fails, it will default to 10Mbps? Could you also check on the PHY reference clock is set to the correct frequency and clock source is stable. Just wondering also whether the PHY drivers are also loaded in Linux (probably ethtool can show this info or via dmesg)Thanks
Regards
Kian
New ContributorHello Kian,
Please see the attached file for the report. I hope you can find something useful in it and assist. I've also included the dmesg log for reference.
dmesg | grep -i phy,
[0.175224] soc:usbphy@0 supply vcc not found, using dummy regulator
[0.811934] socfpga-dwmac ff700000.ethernet: snps,phy-addr property is deprecated
[0.820253] libphy: stmmac: probed
[0.820260] eth0: PHY ID 00221430 at 1 IRQ POLL (stmmac-0:01)
[0.820265] eth0: PHY ID 00221430 at 2 IRQ POLL (stmmac-0:02)
[0.820270] eth0: PHY ID 00221430 at 3 IRQ POLL (stmmac-0:03) active
We need your support
Frequent ContributorHi Jonel,
Thanks for the reply and the background of the request, I'm currently checking with our NA sales team whether they are able to connect to you directly to discuss further.
Thanks
Regards
Kian
New ContributorHello Kian,
I understand that your primary focus is on providing sales support; however, we are in urgent need of technical assistance at the moment, and I hope you understand. I would like to ask a few questions regarding the FPGA code we’re working on. Currently, we are using U-Boot as the boot loader, along with .jic and .rbf for programming. My specific questions are
Our FPGA code for Ethernet is connected to the HPS with an HPS wrapper, whereas in the Intel Eval Kit, the Tri-Speed MAC soft core is used. Is there any advantage to using the Tri-Speed MAC in this case?
Regarding the low-speed results we are seeing, what possible code improvements would you recommend? If feasible, we would also appreciate the opportunity to discuss this further with you.
New ContributorHello Kian,
I’d like to kindly follow up since it has been a few days without a response. We have identified a possible cause of the issue—using ethtool, we observed that the link is running at 10 Mbps half-duplex, even though we intended it to be 100 Mbps full-duplex.
May I ask if Intel could provide guidance on this, particularly regarding the software side and any recommended FPGA driver configurations that might help resolve the issue?
Frequent ContributorHi Jonel1 ,
Sorry for the delay in getting back, have you contacted the local sales people in your region or through our vendors for the Cyclone V board?
Thanks
Regards
Kian
Frequent ContributorHi,
Did you try using this form https://www.altera.com/contact to email our sales representative or distributor network or do you have any specific questions in mind?
Thanks
Regards
Kian
New ContributorDear Intel Team / khtan,
I hope this message finds you well.
Our team in Irving, Texas, has developed a prototype for an Ethernet implementation tailored for avionics design, utilizing the 5CSXFC6D6F31C6N FPGA and the KSZ8873MLL integrated 3-port 10/100 managed switch with PHYs IC. We are currently facing challenges with Ethernet speed performance. We’ve observed that your DK-DEV-5CSXC6N-B evaluation board employs a different PHY, the DP83849CVS/NOPB, which may be relevant to our performance issues.
As we integrate the evaluation board circuitry, we have specific questions about hardware and FPGA code integration to optimize Ethernet performance:
Hardware: Could a technical expert provide detailed insights into the operation of the evaluation board’s PHY circuit and its integration with the FPGA?
FPGA Code: We’ve reviewed sample codes, but they appear tailored for a Renesas PHY IC. Could you provide guidance or resources on adapting these for the TI DP83849CVS/NOPB PHY IC?
To address these challenges thoroughly, we request a meeting with your team to discuss these topics in detail. Any relevant documentation or resources you could share in advance would be greatly appreciated. Please let us know your availability and any preparatory materials we should review.
Thank you for your support. We look forward to your response and arranging a suitable time to connect. Please email me at <email removed for privacy>
