DK-DEV-5CSXC6N-B - Require assistance with technical aspects.

Hi Jonel,

Sorry for the delay, was wondering anyone contacted you as I forwarded your queries to our NA sales/sales tech team as I did not get any reply back from them and we also had a few public holidays on our end.

Anyway for your questions

1. Our FPGA code for Ethernet is connected to the HPS with an HPS wrapper, whereas in the Intel Eval Kit, the Tri-Speed MAC soft core is used. Is there any advantage to using the Tri-Speed MAC in this case?

   Support wise, we have reference design example coverage for Tri Speed MAC and also user guide for it. Tri Speed MAC is also easier to achieve the rated speed .

   2. We have identified a possible cause of the issue—using ethtool, we observed that the link is running at 10 Mbps half-duplex, even though we intended it to be 100 Mbps full-duplex.

   Did you try forcing to 100Mbps using ethtool (eg. ethtool -s eth0 speed 100 duplex full autoneg off to force to 100Mbps to see whether that is achievable) , and could you provide the ethtool report.

   Some possible causes: Assuming no issues with the ethernet cable, is the auto negotiating enabled, or any issues with it as when auto negotiating fails, it will default to 10Mbps? Could you also check on the PHY reference clock is set to the correct frequency and clock source is stable. Just wondering also whether the PHY drivers are also loaded in Linux (probably ethtool can show this info or via dmesg)

Thanks

Regards

Kian