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Altera_Forum's avatar
Altera_Forum
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18 years ago

Disabling Clock signal in FPGA device

Hello,

In my design I have an external clock that feeds sequential logic inside the FPGA. But in some specific situation I want the clock beeing disabled so that the registers are no more updated. I need a global disabling.

One solution is to feed the clock signal in a gate (AND for example), the other AND input will be driven from the enable/disable signal. But I don't know if this solution is really proper inside an FPGA.

Any other idea??

Thanks a lot

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    What device are you using? Are you using a PLL?

    The altclkctrl block in the Megawizard should do what you want. It's controls special logic for getting onto the global, so you don't have to go through general logic for you ANDing function.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    It is best to use a clock enable instead of a gated clock unless you absolutely must shut down the clock to minimize power. The clock enable will stop the registers from toggling and consuming power, but the clock network still dissipates power. The clock enable is all you need for logic functionality.

    If you must shut down the clock to minimize power, use a clock control block for the gating function if your device family has that feature. Use the altclkctrl megafunction to wire up the clock control block.

    Search the forum for posts by me containing "clock enable" for reasons why you should not gate a clock with logic resources. Anything I said about ripple clocks would apply to gated clocks.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    My device is cyclone EP1C3T100C8. I use a PLL but the clock I want to disable is fed through CLK2 pin.

    Brad, by "clock enable" you mean the ENA signal found on every register???

    Whitebird
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    --- Quote Start ---

    ... by "clock enable" you mean the ENA signal found on every register???

    --- Quote End ---

    Yes.

    The Quartus handbook has coding guidelines that show how to write the RTL so that synthesis will infer a clock enable to drive the register ENA input.

    You can also get examples from the text editor templates. In the QII 7.2 text editor, right click and select "Insert Template". Go to "VHDL --> Logic --> Registers" and pick a template labeled with clock enable or a template labeled "with All Secondary Signals".
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hy,

    Maybe you can help me, I would like to know, what happens to signal on output pins (Cyclone II), if global clock failure occurs. I mean if clock signal from quartz somehow disappear. :confused: In my opinion the last state is still on output register.

    Uf one more question what happens if I only use logic blocks and not storage block?

    Regards,

    Primoz