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Altera_Forum
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18 years ago

Disabling Clock signal in FPGA device

Hello, In my design I have an external clock that feeds sequential logic inside the FPGA. But in some specific situation I want the clock beeing disabled so that the registers are no more updat...
Altera_Forum's avatar
Altera_Forum
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18 years ago

What device are you using? Are you using a PLL?

The altclkctrl block in the Megawizard should do what you want. It's controls special logic for getting onto the global, so you don't have to go through general logic for you ANDing function.