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Altera_Forum
Honored Contributor
Honored ContributorDisabling Clock signal in FPGA device
Hello, In my design I have an external clock that feeds sequential logic inside the FPGA. But in some specific situation I want the clock beeing disabled so that the registers are no more updat...
Altera_ForumHonored Contributor
Honored ContributorWhat device are you using? Are you using a PLL?
The altclkctrl block in the Megawizard should do what you want. It's controls special logic for getting onto the global, so you don't have to go through general logic for you ANDing function.
