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Honored ContributorDisabling Clock signal in FPGA device
Hello, In my design I have an external clock that feeds sequential logic inside the FPGA. But in some specific situation I want the clock beeing disabled so that the registers are no more updat...
Altera_ForumHonored Contributor
Honored ContributorMy device is cyclone EP1C3T100C8. I use a PLL but the clock I want to disable is fed through CLK2 pin.
Brad, by "clock enable" you mean the ENA signal found on every register??? Whitebird
