Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorDisabling Clock signal in FPGA device
Hello, In my design I have an external clock that feeds sequential logic inside the FPGA. But in some specific situation I want the clock beeing disabled so that the registers are no more updat...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- ... by "clock enable" you mean the ENA signal found on every register??? --- Quote End --- Yes. The Quartus handbook has coding guidelines that show how to write the RTL so that synthesis will infer a clock enable to drive the register ENA input. You can also get examples from the text editor templates. In the QII 7.2 text editor, right click and select "Insert Template". Go to "VHDL --> Logic --> Registers" and pick a template labeled with clock enable or a template labeled "with All Secondary Signals".
