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Altera_Forum
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18 years ago

Disabling Clock signal in FPGA device

Hello, In my design I have an external clock that feeds sequential logic inside the FPGA. But in some specific situation I want the clock beeing disabled so that the registers are no more updat...
Altera_Forum's avatar
Altera_Forum
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18 years ago

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... by "clock enable" you mean the ENA signal found on every register???

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Yes.

The Quartus handbook has coding guidelines that show how to write the RTL so that synthesis will infer a clock enable to drive the register ENA input.

You can also get examples from the text editor templates. In the QII 7.2 text editor, right click and select "Insert Template". Go to "VHDL --> Logic --> Registers" and pick a template labeled with clock enable or a template labeled "with All Secondary Signals".