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Honored Contributor
Honored ContributorDisabling Clock signal in FPGA device
Hello, In my design I have an external clock that feeds sequential logic inside the FPGA. But in some specific situation I want the clock beeing disabled so that the registers are no more updat...
Altera_ForumHonored Contributor
Honored ContributorHy,
Maybe you can help me, I would like to know, what happens to signal on output pins (Cyclone II), if global clock failure occurs. I mean if clock signal from quartz somehow disappear. :confused: In my opinion the last state is still on output register. Uf one more question what happens if I only use logic blocks and not storage block? Regards, Primoz
