Disabling Clock signal in FPGA device

It is best to use a clock enable instead of a gated clock unless you absolutely must shut down the clock to minimize power. The clock enable will stop the registers from toggling and consuming power, but the clock network still dissipates power. The clock enable is all you need for logic functionality.

If you must shut down the clock to minimize power, use a clock control block for the gating function if your device family has that feature. Use the altclkctrl megafunction to wire up the clock control block.

Search the forum for posts by me containing "clock enable" for reasons why you should not gate a clock with logic resources. Anything I said about ripple clocks would apply to gated clocks.