differential clock output in agilex

Question

Hey!
I want to transmit a differential clock from 1 FPGA to another. I have been looking for a clock output buffer but didn't find it in the IP catalog. I only saw a GPIO IP.
can I use this as a clock buffer? 
or Is it enough to choose a differential pair and assign the clock to the positive pin with "true differential pair" IO standard?

yuanli_s_intel · Answer

If you are using it as output CLOCK, it would be better for you to choose CLOCK related IP such as Clock Control Block (ALTCLKCTRL) or PLL.

ahmad_zaklouta · Answer

ok. Is it enough to connect the output to the positive pin of the differential pair and have the following constraint:

set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to clk_out_p
 
or I should use a GPIO buffer to make it differential?

yuanli_s_intel · Answer

You can use it. However, for clock output, i will still suggest you to use dedicated CLK output pin and also clock related IP for better signal quality.

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differential clock output in agilex

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