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ahmad_zaklouta's avatar
ahmad_zaklouta
Icon for New Contributor rankNew Contributor
3 years ago

differential clock output in agilex

Hey! I want to transmit a differential clock from 1 FPGA to another. I have been looking for a clock output buffer but didn't find it in the IP catalog. I only saw a GPIO IP. can I use this as a ...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

If you are using it as output CLOCK, it would be better for you to choose CLOCK related IP such as Clock Control Block (ALTCLKCTRL) or PLL.



ahmad_zaklouta's avatar
ahmad_zaklouta
Icon for New Contributor rankNew Contributor
3 years ago

ok. Is it enough to connect the output to the positive pin of the differential pair and have the following constraint:

set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to clk_out_p
or I should use a GPIO buffer to make it differential?