different width dual port ram from VHDL template

Dear all,

In my design I have a dual port memory, where the write port is 128x32 configuration and read port is 4096 x 1. I have written the module in the VHDL, but my implementation results in instauration of dual port memory with both ports having 32bits and lots of glue logic around.

When instantiating via megawizard, iget both ports cpnfigured correctly. That brings me a question:

1. What is the proper VHDL template to instantiate different bus width memory

2. How can i te-l to compiler, that this particular entity must be different bus width

3. Is there a way how to tell to compiler to instantiate such memory into m4k memory

4. Itseems that such memory configuration can be write-through instead of pipelines. How that changes the VHDL template?

As for 4. I'm asking because i have some fancy feeling, that when simulating the design, the simulator sometimes simulates the memory as write-through, whereas another times as pipelined.

The relevant piece of code is here. It contains as well some logic calculating number of bits set to 1 in all the memory. This is however irrelevant to issues asked here

http://svnweb.cern.ch/world/wsvn/fimdab/trunk/vhdl/fpga/sources/bunch_selection_memory/bunch_selection_memory.vhd

Thanks for any comment

David