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Honored Contributor
Honored Contributordifferent width dual port ram from VHDL template
Dear all, In my design I have a dual port memory, where the write port is 128x32 configuration and read port is 4096 x 1. I have written the module in the VHDL, but my implementation results in...
Altera_ForumHonored Contributor
Honored ContributorI think I've found some answers (about how to instantiate mix-width dpram) in here:
Recommended HDL Coding Styles, Quartus II 10.1 Handbook - Altera
