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Altera_Forum's avatar
Altera_Forum
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14 years ago

dff with async reset and set got warning of latches on FPGA 3C5

A very simple dff with async reset and preset got warining of latches if I use FPGA 3C5.

module dff(reset, set,clk,d,q);

input reset,set,clk,d;

output q;

reg q;

always@(posedge clk or negedge reset or negedge set)

begin

if(!reset)

q<=0;

else if(!set)

q<=1;

else

q<=d;

end

endmodule

There was no any problem when I use MAXII or MAX V CPLD. But after I switched to FPGA 3C5, I got the warning, as well as FPGA 2C8

"Warning: Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state."

"Warning: Timing Analysis is analyzing one or more combinational loops as latches"

However the simulation result and the actual testing was correct.

My questions are:

1, Why FPGA got this warring but CPLD not ?

2, How to fix it?

Thank you.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    From looking at the logic element block diagram in the respective datasheets, the MAX registers have both asynchronous clear and asynchronous preset, whereas the Cyclone III registers have only asynchronous clear.

    To get an asynchronous clear and preset in Cyclone III, the synthesizer has to use a latch, and tells you with this warning. Best course of action is probably to make one of these control signals synchronous. If you really need them both to be asynchronous, then you can use a synthesis directive to locally turn off the warning.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Tnanks Alias, make sense.

    I changed the verilog code a little bit, the warrning was gone. But the set signal became a sync preset (not a async preset any more)

    module dff(reset, set,clk,d,q);

    input reset,set,clk,d;

    output q;

    reg q;

    always@(posedge clk or negedge reset)

    begin

    if(!reset)

    q<=0;

    else if(!set)

    q<=1;

    else

    q<=d;

    end

    endmodule