dff with async reset and set got warning of latches on FPGA 3C5

Tnanks Alias, make sense.

I changed the verilog code a little bit, the warrning was gone. But the set signal became a sync preset (not a async preset any more)

module dff(reset, set,clk,d,q);

input reset,set,clk,d;

output q;

reg q;

always@(posedge clk or negedge reset)

begin

if(!reset)

q<=0;

else if(!set)

q<=1;

else

q<=d;

end

endmodule