dff with async reset and set got warning of latches on FPGA 3C5

From looking at the logic element block diagram in the respective datasheets, the MAX registers have both asynchronous clear and asynchronous preset, whereas the Cyclone III registers have only asynchronous clear.

To get an asynchronous clear and preset in Cyclone III, the synthesizer has to use a latch, and tells you with this warning. Best course of action is probably to make one of these control signals synchronous. If you really need them both to be asynchronous, then you can use a synthesis directive to locally turn off the warning.