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mthimm2's avatar
mthimm2
Icon for New Contributor rankNew Contributor
4 years ago

Determining Internal Oscillator Frequency on Cyclone V

I'm using the internal oscillator of the Cyclone V as a clock source in a circuit that I'm implementing.

The circuit revolves around the propagation of signals through a series of adders, meant to create delay.

What I've found is that no matter how large of an adder that I make, or how many of them I chain together, the Timing Analyzer reports the same internal oscillator frequency of 30MHz.

I took the time to generate the .sdc file that the compiler requested for design optimization, but I'm now receiving the warning: "Warning (332043): Overwriting existing clock: altera_reserved_tck".

I take this to mean that my critical path is too long and the internal oscillator is too fast to satisfy the relevant timing constraint.

Is there any way to set the internal oscillator frequency or gain more control over it?

Any help is greatly appreciated. I should mention that I'm fairly new to FPGA, in case I've made an obvious, rookie mistake.

3 Replies

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Hi Max,


    What Quartus are you using?

    If you are using current version, there is a feature called design assistant rule check that help you with timing and warning.

    You can enable what rule intended.


  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Hi Maxwell,


    From the attachment. regarding the warning issue, Node: challengeModule:cm|outTerm[0] was determined to be a clock but was found without an associated clock assignment,


    This can be caused in two ways:

    1) A clock assignment was determined to be invalid, so its source objects no longer have a clock associated with them.

    2) When analyzing the netlist, the node was found feeding a clock port with no other clocks feeding it.

    Use the derive_clocks command to automatically find all clock nodes in the design. Also, for any clocks that were ignored, review the warning or error message associated with the command to prevent the clock from being ignored. Specify a clock assignement using create_clock or create_generated_clock tcl command.





  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.