Detailed re-configurable PLL data description for Cyclone 10?

Hi,

Are you referring to latest

https://www.intel.com/content/dam/www/programmable/us/en/video/e2e/pll-reconfiguration-with-mif-file.mp4

Also Refer below links which may help you

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an661.pdf

https://www.intel.com/content/dam/www/programmable/us/en/video/e2e/pll-reconfiguration-with-mif-file.mp4

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

Thanks - that covers exactly, well, zero of my questions.

AN-661 also uses the PLL_RECONFIG block, but does NOT explain the 144 bits that flow between that and the PLL (which is the interface we use). The Appnote does however have a link to a pll_calculator for calculating the charge pump and filters. This sounds like a handy tool - if only the link would not end up in a 404 error.

Our goal is to calculate these 144 bits for a user-given target frequency in order to match that "as close as possible". We don't want to switch between two or three frequencies, but probably at least 20 - and we don't want to keep that many discrete configurations.

Please note that we've been designing with Altera FPGAs since 2002, the days of the Acex 1k series. There's quite a bit of experience in this company, and we would not be asking this question if we had not searched many other sources. So I kindly ask for a little bit more effort - we do have about 130 of these bits explained from a number of sources (including a bit of reverse engineering), but there's still a gap in documentation.

kind regards from Germany,

Jens

*bump*

anyone within Intel with actual knowledge? Documents preferred.

kind regards from Germany,

Jens

Hi @JScho6​ ,

May I know which Cyclone 10 device you using (GX or LP).

Regards,

RS

The exact part number is 10CL006YU256C8G. We've bought a 4-digit quantity through Arrow Germany already, planning to buy a lot more if this re-configurable PLL topic is solved - possibly the slightly-bigger version 10CL010YU256C8G because it has a few more multipliers (RFQ is currently ongoing through Arrow).

I understand that the PLL block is identical between these two, so our decision for the smaller or bigger part does not affect this request for documentation.

thanks,

Jens

RSree, thanks for calling me yesterday. Although I am not a native speaker, I must say that your English will only need a few more years of practise, and you will be able to hold a free conversation. So after 18 minutes, you've found what I already wrote here: The pll reconfiguration calculator link from AN661 is dead:

https://www.intel.com/content/dam/www/programmable/us/en/others/literature/an/PLL_Reconfiguration_Calculator.xlsx

You even wrote another message, confirming that you do not have access to the file in your internal documentation library. I have now done some Googling, and found the file, referenced from yet another Intel page:

https://www.intel.com/content/www/us/en/programmable/support/literature/lit-ip.html

points to:

https://www.intel.com/content/dam/altera-www/global/en_US/others/literature/an/pll_reconfiguration_calculator.xlsx

I just love how Intel respects the valuable time of customers.

Will report back here if the excel sheet answers a few more questions. Right now, Libre office does not show me the source code of the output cells, but that's probably just a setting.

OK, this is starting to get *really* annoying. The document requires a password for the formulas to be viewed. Do I really need to crack the password myself, or are you posting the password here, showing that you actually want to give an answer to a paying customer?

Removing the password and making the fields visible was easy enough. Unfortunately, I can't seem to attach anything here - should anyone be interested in the libre office file to see how the bits are assembled, just contact Jens at icomp.de.

So all this effort comes down to "no, this does not answer the question either", as the Excel sheet does not generate the full 144-bit stream. In fact, it even seems to be incomplete, as I can only select "low" as a bandwidth setting. Is that intentional? Or just a result of "work in progress"?

Anyway, it is hard to believe that we're the only ones wanting to use the re-configurable PLL to it's full extent. I have to label my efforts for finding out the remaining, undocumented bits as "failed", hoping for a clear datasheet to be provided by Intel.

greetings from Germany,

Jens

Yet another *BUMP* - is it really required to praise the Xilinx support, which has answered all our questions within 24 hours so far?

Come on guys, show some effort. This request has been escalated by the app engineers of Arrow Germany as well, and not a single bit of useful information has come across until now.

Another week has passed, and neither Intel, nor Arrow Europe is moving. We've already discovered that the question is too complicated for the India staff to answer, but there *should* be a few persons from the original Altera staff left who know the details. *PLEASE* put one of these on the case - thanks.

Happy Helloween - no need for costumes if you live the horror of bad and missing documentation!

greetings from Germany,

Jens