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JScho6
Occasional Contributor
Occasional ContributorDetailed re-configurable PLL data description for Cyclone 10?
Hi, we're designing a scan rate converter and scaler with an Intel Cyclone 10 FPGA. The output pixel clock shall be configurable, and we've solved a bit of the puzzle, but not all of it yet. As the...
JScho6Occasional Contributor
Occasional ContributorAnother week has passed, and neither Intel, nor Arrow Europe is moving. We've already discovered that the question is too complicated for the India staff to answer, but there *should* be a few persons from the original Altera staff left who know the details. *PLEASE* put one of these on the case - thanks.
Happy Helloween - no need for costumes if you live the horror of bad and missing documentation!
greetings from Germany,
Jens
