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JScho6's avatar
JScho6
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Detailed re-configurable PLL data description for Cyclone 10?

Hi, we're designing a scan rate converter and scaler with an Intel Cyclone 10 FPGA. The output pixel clock shall be configurable, and we've solved a bit of the puzzle, but not all of it yet. As the...
JScho6's avatar
JScho6
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Removing the password and making the fields visible was easy enough. Unfortunately, I can't seem to attach anything here - should anyone be interested in the libre office file to see how the bits are assembled, just contact Jens at icomp.de.

So all this effort comes down to "no, this does not answer the question either", as the Excel sheet does not generate the full 144-bit stream. In fact, it even seems to be incomplete, as I can only select "low" as a bandwidth setting. Is that intentional? Or just a result of "work in progress"?

Anyway, it is hard to believe that we're the only ones wanting to use the re-configurable PLL to it's full extent. I have to label my efforts for finding out the remaining, undocumented bits as "failed", hoping for a clear datasheet to be provided by Intel.

greetings from Germany,

Jens