Detailed re-configurable PLL data description for Cyclone 10?

Thanks - that covers exactly, well, zero of my questions.

AN-661 also uses the PLL_RECONFIG block, but does NOT explain the 144 bits that flow between that and the PLL (which is the interface we use). The Appnote does however have a link to a pll_calculator for calculating the charge pump and filters. This sounds like a handy tool - if only the link would not end up in a 404 error.

Our goal is to calculate these 144 bits for a user-given target frequency in order to match that "as close as possible". We don't want to switch between two or three frequencies, but probably at least 20 - and we don't want to keep that many discrete configurations.

Please note that we've been designing with Altera FPGAs since 2002, the days of the Acex 1k series. There's quite a bit of experience in this company, and we would not be asking this question if we had not searched many other sources. So I kindly ask for a little bit more effort - we do have about 130 of these bits explained from a number of sources (including a bit of reverse engineering), but there's still a gap in documentation.

kind regards from Germany,

Jens