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JScho6
Occasional Contributor
Occasional ContributorDetailed re-configurable PLL data description for Cyclone 10?
Hi, we're designing a scan rate converter and scaler with an Intel Cyclone 10 FPGA. The output pixel clock shall be configurable, and we've solved a bit of the puzzle, but not all of it yet. As the...
JScho6Occasional Contributor
Occasional ContributorYet another *BUMP* - is it really required to praise the Xilinx support, which has answered all our questions within 24 hours so far?
Come on guys, show some effort. This request has been escalated by the app engineers of Arrow Germany as well, and not a single bit of useful information has come across until now.
