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JScho6's avatar
JScho6
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Detailed re-configurable PLL data description for Cyclone 10?

Hi, we're designing a scan rate converter and scaler with an Intel Cyclone 10 FPGA. The output pixel clock shall be configurable, and we've solved a bit of the puzzle, but not all of it yet. As the...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

Are you referring to latest

https://www.intel.com/content/dam/www/programmable/us/en/video/e2e/pll-reconfiguration-with-mif-file.mp4

Also Refer below links which may help you

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an661.pdf

https://www.intel.com/content/dam/www/programmable/us/en/video/e2e/pll-reconfiguration-with-mif-file.mp4

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)