Design won't fit in device

hi,

the problem may be a memory problem, if you used a lot of memory space.

good luck

Thanks for the reply.

I think the design started out not using memory but then memory was used to cut down the size of some very large fifo's. I was curious about the how the fitter may see things i.e. if it doesn't see, say, 20% of the device empty, it won't attempt to fit.

OK, sometimes the design occupies 20% and place and route fail, because there are resources such as memory cells or DSP are used by design!

then tchek that the report gives the fitter to see the resources are fully utilized.

good luck

Hi,

Your resource problem is the logic, not memory blocks as indicated by the error message(LABs).

The notion of 85% or so is sort of rule of thumb for fmax. The fitter doesn't follow this rule. It will fit as long as there is resource until 100% if necessary.

Kaz

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Hi,

Your resource problem is the logic, not memory blocks as indicated by the error message(LABs).

The notion of 85% or so is sort of rule of thumb for fmax. The fitter doesn't follow this rule. It will fit as long as there is resource until 100% if necessary.

Kaz

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What settings are using ? E.g. optimize for speed or physical synthesis ....

Some settings:

1. physical_synthesis_map_logic_to_memory_for_area = on

2. physical_synthesis_combo_logic_for_area = on

3. fmax is set to 125MHz

4. mux_restructure = on

5. allow_any_ram_size_for_recognition = on

6. allow_any_rom_size_for_recognition = on

7. allow_any_shift_register_size_for_recognition = on

8. auto_packed_registers_stratixii = minimise area

9. fitter_effort = standard fit

10. router_effort_multuplier = 2.0

11. router_timing_optimization_level = maximum

12. partition_fitter_preservation_level = placement and routing

13. smart_recompile = on

15. stratixii_optimisation_technique = area

It takes several hours just to get to the fitter stage.

Regards

MT

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Some settings:

1. physical_synthesis_map_logic_to_memory_for_area = on

2. physical_synthesis_combo_logic_for_area = on

3. fmax is set to 125MHz

4. mux_restructure = on

5. allow_any_ram_size_for_recognition = on

6. allow_any_rom_size_for_recognition = on

7. allow_any_shift_register_size_for_recognition = on

8. auto_packed_registers_stratixii = minimise area

9. fitter_effort = standard fit

10. router_effort_multuplier = 2.0

11. router_timing_optimization_level = maximum

12. partition_fitter_preservation_level = placement and routing

13. smart_recompile = on

15. stratixii_optimisation_technique = area

It takes several hours just to get to the fitter stage.

Regards

MT

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Hi,

are you using design partitions in your Quartus project ? If, yes try a run where you remove all design partitions. Another reason could be memory description which are not recognized or could not implemented in the memory of the FPGA. So have look to the to the compilation report : Analysis & Synthesis -> Resource Uitlization by Entity

Are memory and DSP blocks (e.g.) used etc......

Thanks for the info.

From what I can see in the report, block memory is being used. However, no DSP blocks are being used.

I don't know much about the design at this stage as I've added some logic to it at a very low level, so, I'm finding my way round it too. I don't know what this 'partition_fitter_preservation_level' refers to. I would like to try it completely flattened with no incremental synthesis or anything like that. Right now, I just want it to fit.

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Fitter Preservation Level: Allows you to specify the amount of information that you want the Fitter to preserve from the specified netlist file. Fitter Preservation Level is only available when Full incremental compilation is turned on.

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Does the design fit into the FPGA before you changed it ?