Design won't fit in device

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Some settings:

1. physical_synthesis_map_logic_to_memory_for_area = on

2. physical_synthesis_combo_logic_for_area = on

3. fmax is set to 125MHz

4. mux_restructure = on

5. allow_any_ram_size_for_recognition = on

6. allow_any_rom_size_for_recognition = on

7. allow_any_shift_register_size_for_recognition = on

8. auto_packed_registers_stratixii = minimise area

9. fitter_effort = standard fit

10. router_effort_multuplier = 2.0

11. router_timing_optimization_level = maximum

12. partition_fitter_preservation_level = placement and routing

13. smart_recompile = on

15. stratixii_optimisation_technique = area

It takes several hours just to get to the fitter stage.

Regards

MT

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Hi,

are you using design partitions in your Quartus project ? If, yes try a run where you remove all design partitions. Another reason could be memory description which are not recognized or could not implemented in the memory of the FPGA. So have look to the to the compilation report : Analysis & Synthesis -> Resource Uitlization by Entity

Are memory and DSP blocks (e.g.) used etc......