Design won't fit in device

Yes, it did. I've disabled most of the logic that I added and kept it to it's minimum. I've tried many combinations of options and the best ones (as usual the original ones) puts the design 18 labs too big.

Does Quartus do multiple attempts if it fails to fit? Is there a way of finding out quickly that it's likely to fail?

If the report suggests that there are enough LEs but too few LABs then it's probably a routing problem rather than a logic problem. Enabling the automatic insertion of logic and registers can help this.

Tools>>Advisors>> Resource Optimisation Advisor might help - there's a section there on routing resource.

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Yes, it did. I've disabled most of the logic that I added and kept it to it's minimum. I've tried many combinations of options and the best ones (as usual the original ones) puts the design 18 labs too big.

Does Quartus do multiple attempts if it fails to fit? Is there a way of finding out quickly that it's likely to fail?

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The fitter tries a maximum of 3 placement and routing attempts, with each successive attempt increasing the placement effort and hence increasing compilation times. You can

limit it to one attempt.

Settings -> Fitter Settings -> Limit to one fitting attempt

When the design fits, what was the device utilization, the peak and the average routing usage ?

What kind of design is it ? Digital signal processing ????

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I get an error saying that the fitter requires 13555 LABs to implement but device only contains 13520 LABs.

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If the report suggests that there are enough LEs but too few LABs then it's probably a routing problem rather than a logic problem.

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I think I've never known of this kind of no-fit error being related to routing other than at the LAB control signal level. The device handbook documents how many clocks, clock enables, asynchronous clears, etc. are available in each LAB. For example, a device might support only two clock enables in a LAB. If the Fitter has placed two registers in the LAB using two different clock enables, then the Fitter can't place any registers in that LAB using any other clock enable. When the "Control Signals" table in the Fitter report lists a huge number of one of these categories of signals (typically it will be clock enables), this device restriction can make it difficult or impossible for the Fitter to group registers into few enough LABs to fit. This can happen even when the logic utilization is well below 100%.

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We've solved this one now. Not all the FIFO's we're using block ram - some use registers because it's move efficient. Altering that ratio - putting more in block memory solved the problem.

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Great, when you look to the resources for the entities did you see an unusual ratio between the number of LCELL and Registers for the block where the Fifos are in ?

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Hi,

Your resource problem is the logic, not memory blocks as indicated by the error message(LABs).

The notion of 85% or so is sort of rule of thumb for fmax. The fitter doesn't follow this rule. It will fit as long as there is resource until 100% if necessary.

Kaz

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Hi

I do have a problem with compilation when setting the on-chip RAM to 60kb on a Cyclone 3c25. I once did that and the project compiled without any problem. But now it wont work even in a simple project. I only intend to use on-chip memory to use 'fopen' and 'fclose' in my C code. I dont know what could be the problem if it did work once. Please help.