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MartinMaa's avatar
MartinMaa
Icon for Occasional Contributor rankOccasional Contributor
1 month ago
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Dedicated Clock Pins for MAX 10

Hello Intel Community,   I am currently designing a system using the Intel MAX 10 FPGA, specifically the 10M02SCM153C8G in the compact M153 micro-package. Due to the highly constrained pin resource...
Core Logic
Programmable Logic Device
  • FvM's avatar
    FvM
    1 month ago

    Hi Martin, 

    Pin Planner info is correct. Please compare with your previous post that confuses in- and outputs. Only difference is wheter PIN_L1 (outclk_n) can be alternatively used as single ended dedicated clock output. According to Quartus compilation result it can.

    Regards Frank

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 month ago

Hi Martin, 

Pin Planner info is correct. Please compare with your previous post that confuses in- and outputs. Only difference is wheter PIN_L1 (outclk_n) can be alternatively used as single ended dedicated clock output. According to Quartus compilation result it can.

Regards Frank

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    Thank you, Frank, for the replies.

     

    Hi Martin,

     

    Do you have any other questions on top of Frank's reply?

     

    Regards,
    Aqid