Forum Discussion
Occasional ContributorDedicated Clock Pins for MAX 10
Hi Martin,
Pin Planner info is correct. Please compare with your previous post that confuses in- and outputs. Only difference is wheter PIN_L1 (outclk_n) can be alternatively used as single ended dedicated clock output. According to Quartus compilation result it can.
Regards Frank
Super ContributorHi Martin,
"Pins J4, J5, K4, and K5 can be used as PLL OUTPUTs.
Pin P2 can be used as a PLL INPUT."
No and no, it's the other way around.
As I mentioned, PIN_N1 is the other dedicated PLL output of 10M02SC153. If you are not obliged to achieve lowest jitter and skew, you can route PLL output to any IO pin and also use other dedicated clock inputs not directly routed to PLL1, e.g. CLK[2,3][p,n].
Regards Frank
Occasional ContributorHi Frank,
I’m a bit confused now. In the Pin Planner, when I select the PLL1 option in the report, what is the meaning of the pins enclosed by the bold black box? If they do not represent the input and output pins of PLL1, then what are they?
After I select the checkbox, it specifically highlights these pins by enclosing them within a bold black box.
My application is quite simple, utilizing only an SCFIFO and some integrated peripheral logic circuits. However, if the FPGA has sufficient resources, I would like to optimize its utilization to the best possible state, as I may implement a 50MHz application in the future.
