Forum Discussion
Occasional ContributorDedicated Clock Pins for MAX 10
Hi Martin,
Pin Planner info is correct. Please compare with your previous post that confuses in- and outputs. Only difference is wheter PIN_L1 (outclk_n) can be alternatively used as single ended dedicated clock output. According to Quartus compilation result it can.
Regards Frank
Occasional ContributorHi Frank.
I have a quick question regarding the Pin Planner. If I check these two specific options in the Report panel, do the pins outlined with a thick black box in the Top View represent the actual dedicated pins for PLL1?
FvMSuper Contributor
Hi Martin,
you are correct. PIN_N1 can be additionally used as single ended clock output. CLK[6,7] pins mentioned in my previous post aren't available for 10M02.
Regards
Frank- MartinMaa
Hi Frank,
Sorry, I’ve been thinking about this and I still have a few questions.
I didn't mention PIN_N1 earlier, and N1 is not used in my design.
Alternatively, could you directly clarify if the bold black boxes shown in the Pin Planner interface (with the "Report" option checked on the top left for PLL INPUT and PLL OUTPUT) represent the available PLL pins for this FPGA?
For example, based on this diagram:
Pins J4, J5, K4, and K5 can be used as PLL OUTPUTs.
Pin P2 can be used as a PLL INPUT.
Is my understanding correct? Thank you.
