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MartinMaa's avatar
MartinMaa
Icon for Occasional Contributor rankOccasional Contributor
13 days ago
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Dedicated Clock Pins for MAX 10

Hello Intel Community,   I am currently designing a system using the Intel MAX 10 FPGA, specifically the 10M02SCM153C8G in the compact M153 micro-package. Due to the highly constrained pin resource...
Core Logic
Programmable Logic Device
  • FvM's avatar
    FvM
    5 days ago

    Hi Martin, 

    Pin Planner info is correct. Please compare with your previous post that confuses in- and outputs. Only difference is wheter PIN_L1 (outclk_n) can be alternatively used as single ended dedicated clock output. According to Quartus compilation result it can.

    Regards Frank

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
11 days ago

Hi Martin,

your questions are basically answered in MAX10 Device Handbook and Pinout documents. Your device has only PLL1 (left side) and one pair of dedicated clockout pins. Dedicated input pins for PLL1 are CLK[0,1][p,n] and CLK[6,7][p,n], but not CLK2p pin J12 selected in your design. Also pin K4 is no dedicated clockout pin. Depending on your application, non-dedicated clock routing warnings can be possibly ignored.

Regards Frank