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Altera_Forum's avatar
Altera_Forum
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15 years ago

Debouncer verilog code

Hi you

I wrote a simple code for a debouncer circuit, and I appreciate if you can have a look and correct what's wrong. 


module debouncer (noisy,clk_1KHz,debounced);
input wire clk_1KHz, noisy;
output wire debounced;
reg  cnt;
//counter: waits that button is pressed at least 10ms 
always @ (posedge clk_1KHz) 
begin
if (noisy) cnt <= cnt + 1'b1;
else cnt <= 0;
end
assign debounced = (cnt==4'b1010) ? 1'b1 : 1'b0;
endmodule
what you think about it?:confused:

thank you all

GP

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    
module debouncer (noisy,clk_1KHz,debounced);
input wire clk_1KHz, noisy;
output reg debounced;
reg  reg;
//reg: wait for stable
always @ (posedge clk_1KHz) 
begin
reg <= {reg,noisy}; //shift register
if(reg == 8'b00000000)
  debounced <= 1'b0;
else if(reg == 8'b11111111)
  debounced <= 1'b1;
else debounced <= debounced;
end
endmodule

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    dear ARTEM_BOND,

    I read your post, and I found their brilliant solution!

    I'm trying to build a simple and efficient verilog code, to solve the problem of noise...

    I made the following modification in your code, hoping to get a greater number of shifts: 

    
 module debouncer (noisy, clock, debounced);
 input wire clock, noisy;
 output reg debounced;
 parameter M = 8;
 reg  reg;
 //reg: wait for stable
 always @ (posedge clock) 
 begin
   reg <= {reg,noisy}; // N shift register
   if(reg == (2**M)*0)
     debounced <= 1'b0;
   else if(reg == (2**M)-1)
     debounced <= 1'b1;
   else debounced <= debounced;
 end
 endmodule

    I think something is wrong in the code because I can notice any noise,

    by oscilloscope, even increased the value of M.

    Could you help me with this?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Couple of suggestions:

    (1) Instead of doing: 

    (reg == (2**M)*0)

    you could do: 

    (~|reg)

    And similarly for: 

    (reg == (2**M)-1)

    do: 

    (&reg)

    Personally I think it looks cleaner.

    (2) It is really not a good idea to call a register 'reg'. 'reg' is a reserved keyword and should be used as the name. Perhaps a better name would be: 

    reg  shift;

    Or something similar.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    dear TCWORLD,

    I would like to clarify that this code is written by the

    Altera Teacher ARTEM_BOND and "reg" is authored by himself.

    I left exactly as he wrote, to not cause confusion.

    Below is my code which coincidentally, was exactly the name I used: 

    
module debounce(
    input wire clock,
    input wire IN,
    output reg OUT
);
 parameter M = 8;
 reg shift;
 //shift: wait for stable
 always @ (posedge clock) 
 begin
   shift <= {shift,IN}; // N shift register
// if(shift == (2**M)*0)
   if(~|shift)
     OUT <= 1'b0;
// else if(shift == (2**M)-1)
   else if(&shift)
     OUT <= 1'b1;
   else OUT <= OUT;
 end
 endmodule

    If I understand correctly what you suggested, their changes are only to make the code cleaner...

    It really was it, nothing worked to help me, because nothing was fixed!!!

    As I requested earlier:

    ..."I think something is wrong in the code because I can notice any noise,

    by oscilloscope, even increased the value of M.

    Could you help me with this?"

    (Excuse me if not expressed myself correctly, my English is not very good.)
    • sintech's avatar
      sintech
      Icon for New Contributor rankNew Contributor
      5 years ago

      For someone who found this topic looking for a working debouncer.

      The correct code:

      module debounce(
    input wire clock,
    input wire IN,
    output reg OUT
);
 parameter M = 8;
 reg [M:0]shift;
 //shift: wait for stable
 always @ (posedge clock) 
 begin
   shift <= {shift,IN}; // N shift register
   if(~|shift)
     OUT <= 1'b0;
   else if(&shift)
     OUT <= 1'b1;
   else OUT <= OUT;
 end
 endmodule