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Honored Contributor
Honored ContributorDebouncer verilog code
Hi you I wrote a simple code for a debouncer circuit, and I appreciate if you can have a look and correct what's wrong.
module debouncer (noisy,clk_1KHz,debounced);
input wire clk_1KHz...
Altera_ForumHonored Contributor
Honored Contributor
module debouncer (noisy,clk_1KHz,debounced);
input wire clk_1KHz, noisy;
output reg debounced;
reg reg;
//reg: wait for stable
always @ (posedge clk_1KHz)
begin
reg <= {reg,noisy}; //shift register
if(reg == 8'b00000000)
debounced <= 1'b0;
else if(reg == 8'b11111111)
debounced <= 1'b1;
else debounced <= debounced;
end
endmodule
