Debouncer verilog code

dear TCWORLD,

I would like to clarify that this code is written by the

Altera Teacher ARTEM_BOND and "reg" is authored by himself.

I left exactly as he wrote, to not cause confusion.

Below is my code which coincidentally, was exactly the name I used:

module debounce(
    input wire clock,
    input wire IN,
    output reg OUT
);
 parameter M = 8;
 reg shift;
 //shift: wait for stable
 always @ (posedge clock) 
 begin
   shift <= {shift,IN}; // N shift register
// if(shift == (2**M)*0)
   if(~|shift)
     OUT <= 1'b0;
// else if(shift == (2**M)-1)
   else if(&shift)
     OUT <= 1'b1;
   else OUT <= OUT;
 end
 endmodule

If I understand correctly what you suggested, their changes are only to make the code cleaner...

It really was it, nothing worked to help me, because nothing was fixed!!!

As I requested earlier:

..."I think something is wrong in the code because I can notice any noise,

by oscilloscope, even increased the value of M.

Could you help me with this?"

(Excuse me if not expressed myself correctly, my English is not very good.)