Debouncer verilog code

dear ARTEM_BOND,

I read your post, and I found their brilliant solution!

I'm trying to build a simple and efficient verilog code, to solve the problem of noise...

I made the following modification in your code, hoping to get a greater number of shifts:

 module debouncer (noisy, clock, debounced);
 input wire clock, noisy;
 output reg debounced;
 parameter M = 8;
 reg  reg;
 //reg: wait for stable
 always @ (posedge clock) 
 begin
   reg <= {reg,noisy}; // N shift register
   if(reg == (2**M)*0)
     debounced <= 1'b0;
   else if(reg == (2**M)-1)
     debounced <= 1'b1;
   else debounced <= debounced;
 end
 endmodule
 

I think something is wrong in the code because I can notice any noise,

by oscilloscope, even increased the value of M.

Could you help me with this?