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Altera_Forum's avatar
Altera_Forum
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12 years ago

DDR3 discret component skew question

Hi all,

I'm designing a new board based on an ARRIA V with 2 DDR3 component. Both of them are x16 DQ. I routed CLK, address and command as T-topology.

I want to use the Hard External Memory Interface (EMIF) running at 533MH (1066Mbps).

I read many times the Altera "Design Layout Guidelines", however, I didn't find length-matching rule I have to follow between byte-lane group. Does anybody know that ?

In other words :

DM0 DQS0 DQ00..DQ07 must have + or - 1.27mm of deviation but between DM0 and DM1, what is the maximum deviation ?

I've got the same question between byte lane group and Clock ?

Thanks in advance.

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I didn't explain my problem very well, you misunderstand me :

    I'm looking for the max deviation between byte-groups ?

    I'm, also, looking for the max deviation between byte-groups and clocks ?

    I find in the Board Skew Parameter Tool :

    - the max deviation between byte-groups is 1 ns (according to me it's + or - 158 mm).

    - the max deviation between byte-groups and clock is 0ps?!!? (I think that's mean that byte-groups track have to be shorter than clocks track.)

    Is that correct ?
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    I find in the Board Skew Parameter Tool :

    - the max deviation between byte-groups is 1 ns (according to me it's + or - 158 mm).

    --- Quote End ---

    Yes! In the screenshot - second box from top notes this. I just stuck some values there to get this screenshot in the tool. The values in the green/orange boxes are not accurate at all. But you can see the min/max allowable values next to the boxes.

    --- Quote Start ---

    - the max deviation between byte-groups and clock is 0ps?!!? (I think that's mean that byte-groups track have to be shorter than clocks track.)

    Is that correct ?

    --- Quote End ---

    In the screenshot 0ps is indicated as min value. i.e. tpd-clk > tpd-dqs.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Micron have an application note TN-41-13 (DDR point to point design) which is useful here. Under the Trace Length Matching heading, the note suggests that wasting up to 1% (+/-0.5% arbitrarily) of the total timing budget on length matching is appropriate. With 533 Mhz clock, that is 9.4 ps (1876ps/200). Typical FR4 flight time is 6.5 ps/mm. So this suggests you need to length match to better than +/-1.4 mm. Is this the answer to your question? All signal lines should be the same length.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I found another reference by chance in the Altera External Memory Interface Handbook, Vol 3, Assumptions p1-46:

    This assumption requires that DQ-to-DQS skews be within the recommended 20 ps.

    So it must be better than +/-1.5mm.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    We have a working board using 4 x DDR3 RAMS (64M x 16), and documented it under the post

    'DDR3 IP with Uniphy PLL_AFI_CLK timing closure problems'.

    It works using a soft controller.

    We have skew between all signal lines of less than +/-5.6ps. In our calibrated margin report we see a variation of up to 75ps (3 adjustment bins) in the position of the read and write windows. Much of this must be down to cross talk, and noise. In the uncalibrated margin report we see a variation of up to 325 ps - which is probably pin driver delay variation in the Arria V.

    I guess that means you can have a bit more variation in the skew, but any that you have reduces the margin you can tolerate in other areas.