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Altera_Forum
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12 years ago

DDR3 discret component skew question

Hi all, I'm designing a new board based on an ARRIA V with 2 DDR3 component. Both of them are x16 DQ. I routed CLK, address and command as T-topology. I want to use the Hard External Memory Int...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Micron have an application note TN-41-13 (DDR point to point design) which is useful here. Under the Trace Length Matching heading, the note suggests that wasting up to 1% (+/-0.5% arbitrarily) of the total timing budget on length matching is appropriate. With 533 Mhz clock, that is 9.4 ps (1876ps/200). Typical FR4 flight time is 6.5 ps/mm. So this suggests you need to length match to better than +/-1.4 mm. Is this the answer to your question? All signal lines should be the same length.