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Altera_Forum
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13 years ago

DDR3 discret component skew question

Hi all, I'm designing a new board based on an ARRIA V with 2 DDR3 component. Both of them are x16 DQ. I routed CLK, address and command as T-topology. I want to use the Hard External Memory Int...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I didn't explain my problem very well, you misunderstand me :

I'm looking for the max deviation between byte-groups ?

I'm, also, looking for the max deviation between byte-groups and clocks ?

I find in the Board Skew Parameter Tool :

- the max deviation between byte-groups is 1 ns (according to me it's + or - 158 mm).

- the max deviation between byte-groups and clock is 0ps?!!? (I think that's mean that byte-groups track have to be shorter than clocks track.)

Is that correct ?