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Honored Contributor
Honored ContributorDDR3 discret component skew question
Hi all, I'm designing a new board based on an ARRIA V with 2 DDR3 component. Both of them are x16 DQ. I routed CLK, address and command as T-topology. I want to use the Hard External Memory Int...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I find in the Board Skew Parameter Tool : - the max deviation between byte-groups is 1 ns (according to me it's + or - 158 mm). --- Quote End --- Yes! In the screenshot - second box from top notes this. I just stuck some values there to get this screenshot in the tool. The values in the green/orange boxes are not accurate at all. But you can see the min/max allowable values next to the boxes. --- Quote Start --- - the max deviation between byte-groups and clock is 0ps?!!? (I think that's mean that byte-groups track have to be shorter than clocks track.) Is that correct ? --- Quote End --- In the screenshot 0ps is indicated as min value. i.e. tpd-clk > tpd-dqs.
