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Honored Contributor
Honored ContributorDDR3 discret component skew question
Hi all, I'm designing a new board based on an ARRIA V with 2 DDR3 component. Both of them are x16 DQ. I routed CLK, address and command as T-topology. I want to use the Hard External Memory Int...
Altera_ForumHonored Contributor
Honored ContributorWe have a working board using 4 x DDR3 RAMS (64M x 16), and documented it under the post
'DDR3 IP with Uniphy PLL_AFI_CLK timing closure problems'. It works using a soft controller. We have skew between all signal lines of less than +/-5.6ps. In our calibrated margin report we see a variation of up to 75ps (3 adjustment bins) in the position of the read and write windows. Much of this must be down to cross talk, and noise. In the uncalibrated margin report we see a variation of up to 325 ps - which is probably pin driver delay variation in the Arria V. I guess that means you can have a bit more variation in the skew, but any that you have reduces the margin you can tolerate in other areas.
