DDR Interface SDC Constraint

I can not read your sdc.txt because I'm sitting behind a firewall/gateway blocking that.

But I have the idea that you are driving the transmit clock directly from the PLL (that is what your schematic shows). This can never meet timing because it takes the data quite some time arriving at the pin.

May I suggest you to drive the tx clock out with a DDROUT block as well.

In your sdc create a generated clock for this pin and use this as the clock in your set_output_delay constraints for the data outputs.

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Does TQ give you any warnings (besides obvious "critical warning:timing requirements not met)?

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There is no other warning given by TQ.

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Your refer to clock or data? Can you explain it more details?

Thanks

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Your refer to clock or data? Can you explain it more details?

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I deduced from your drawing that the 90degree tx clock is a direct pll output onto a dedicated pin. This has little delay from source (pll) to output (pin). (Even more, if you compensated the PLL to this output pin the delay is virtually 0). But the data goes through a combinatorial multiplexer and thus sees more delay before it reaches the pin. That's why I suggested to drive the tx clock using a DDROUT as well. Then the 90 degree output clock incurs 'identical' delays as incurred by the data.