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Altera_Forum's avatar
Altera_Forum
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15 years ago

DDR Interface SDC Constraint

Hi. I have written a constraint on DDR interface. When I run timing analysis, it shows that it fail in setup time. Based on the ddr example I have seen, it runs at 400MHz. So, my ddr ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Does TQ give you any warnings (besides obvious "critical warning:timing requirements not met)?

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There is no other warning given by TQ.

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Your refer to clock or data? Can you explain it more details?

Thanks