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Your refer to clock or data? Can you explain it more details?
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I deduced from your drawing that the 90degree tx clock is a direct pll output onto a dedicated pin. This has little delay from source (pll) to output (pin). (Even more, if you compensated the PLL to this output pin the delay is virtually 0). But the data goes through a combinatorial multiplexer and thus sees more delay before it reaches the pin. That's why I suggested to drive the tx clock using a DDROUT as well. Then the 90 degree output clock incurs 'identical' delays as incurred by the data.
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