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Altera_Forum's avatar
Altera_Forum
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14 years ago

DDR Interface SDC Constraint

Hi. I have written a constraint on DDR interface. When I run timing analysis, it shows that it fail in setup time. Based on the ddr example I have seen, it runs at 400MHz. So, my ddr ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I can not read your sdc.txt because I'm sitting behind a firewall/gateway blocking that.

But I have the idea that you are driving the transmit clock directly from the PLL (that is what your schematic shows). This can never meet timing because it takes the data quite some time arriving at the pin.

May I suggest you to drive the tx clock out with a DDROUT block as well.

In your sdc create a generated clock for this pin and use this as the clock in your set_output_delay constraints for the data outputs.