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Altera_Forum
Honored Contributor
Honored ContributorDDR input without DPA in Arria II GX
Hello
I am using arria ii gx to communicate with a high speed device. The device is sending DDR data, data with a data clock, dclk. dclk and data are source synchronous. I need to capture the data inside my Arria II GX FPGA, using dclk and separate it into a positive & negative edge streams. The problem is that the skew between dclk and data, by the time they get into the FPGA, is unknown. Thus I want to be able to slide dclk or try different phases of dclk to capture the data. I was able to do this in Xilinx Virtex FPGAs using the iobdelay function, which allowed me to adjust the skew between dclk and data at run time. I want to do exactly the same in Arria II GX but I find no comparable option. I do not have a training pattern so the dpa is out. Can someone suggest a solution? Can I gain the ability to try various phases of dclk for sampling data in Arria II GX? Thanks in advance for your help!!!26 Replies
Altera_ForumThat's what I would try.
Jake- Altera_Forum
Jake
I know Stratix has that feature. Unfortunately, I need to find a way of achieving it on Arria II GX. The PLL dynamic phase change looks promising. But I will be limited to only 8 possible phases because M=1, N=1 would make the VCO frequency same as input frequency and thus I would loose the 'fine tuning' that would have been available if my VCO frequency were higher. Do you think the following scheme can work? ** Use a PLL ** PLL ref clock is DDR input clock ** PLL in normal mode ** M=N=1 ** PLL output clock is used to sample input data ** Use Dynamic Phase shifting inputs of PLL to move PLL output clock to optimum sampling position Regards - Altera_Forum
The Stratix IV does have programmable IO delays but Arria II GX does not.
Jake - Altera_Forum
FvM
IDELAY in Xilinx allows delays in multiples of 50ps to be inserted in an I/O pad and that is what I meant. My apologies for using incorrect word. Regard, - Altera_Forum
Jake
The DDR clock and data from the device will come into the FPGA when the FPGA board is connected to the other board. However, I plan to run the FPGA using a clock from an on-board (FPGA board) oscillator. That should not be a problem, right? - Altera_Forum
Looks like both FvM and I have brought up the dynamic phase shifting of the PLL. I'm thinking that's what you ought to look into. Again though, you're going to have to be able to dynamically reconfigure. I'll again pose the question. Is the clock input always present?
Jake - Altera_Forum
Your question is partly based on wrong assumptions. DPA doesn't require a train pattern, it only requires signal edges to be present during the adjustment. Without signal edges, you can perform no adjustment at all. A train pattern is needed for adjustment of the SERDES bit slip feature (shifting by integer bit clock intervals), but you can also control it manually or disable it.
DPA does however need a PLL, and this also means implicitely a fixed frequency (respectively a small guaranteed lock range). So dynamic reconfiguration is necessary to achieve a wider frequency range. Instead of DPA, which is adjusting the receive phase automaticly (and keeping it on request), PLL dynamic phase shift is also available with Arria II. It allows a manual stepwise control of a clock phase. Logic cell delay, variable e.g. through a multilplexer would allow a limited range, step wise phase adjustment without depending on a particular clock frequency. Logic cell delays aren't well specified and also temperature dependant, in so far they perfectly complement your loosely specified clock. P.S.: IOBDELAY with Xilinx is, as far as I understand a constraint parameter, not variable at runtime. - Altera_Forum
Is the clock always present such that it can be used as a PLL input?
- Altera_Forum
Jake,
Its not that nothing is known. For each board, the frequency of the clock coming in as well as its relationship to the data bus is known; its just that both of these are changing from board to board. To create a separate bitstream for each board is not feasible, so my goal is to build a design in which I can vary the skew between data and clock before it gets sampled by the input DDR cells. Hit and trial by user (granted an ability to play around with the skew adjustment), until data is correctly sampled, is acceptable. Thank you very much for your kind and generous help! - Altera_Forum
So the skew actually changes from board to board? And your frequency is unknown?
Well this is quite the interface you've got. A high-speed source-synchronous interface with absolutely no deterministic qualities. What things are known about the interface that we can make use of? Jake
