DDR input without DPA in Arria II GX

Jake,

Its not that nothing is known. For each board, the frequency of the clock coming in as well as its relationship to the data bus is known; its just that both of these are changing from board to board. To create a separate bitstream for each board is not feasible, so my goal is to build a design in which I can vary the skew between data and clock before it gets sampled by the input DDR cells. Hit and trial by user (granted an ability to play around with the skew adjustment), until data is correctly sampled, is acceptable.

Thank you very much for your kind and generous help!