DDR input without DPA in Arria II GX

Your question is partly based on wrong assumptions. DPA doesn't require a train pattern, it only requires signal edges to be present during the adjustment. Without signal edges, you can perform no adjustment at all. A train pattern is needed for adjustment of the SERDES bit slip feature (shifting by integer bit clock intervals), but you can also control it manually or disable it.

DPA does however need a PLL, and this also means implicitely a fixed frequency (respectively a small guaranteed lock range). So dynamic reconfiguration is necessary to achieve a wider frequency range. Instead of DPA, which is adjusting the receive phase automaticly (and keeping it on request), PLL dynamic phase shift is also available with Arria II. It allows a manual stepwise control of a clock phase.

Logic cell delay, variable e.g. through a multilplexer would allow a limited range, step wise phase adjustment without depending on a particular clock frequency. Logic cell delays aren't well specified and also temperature dependant, in so far they perfectly complement your loosely specified clock.

P.S.: IOBDELAY with Xilinx is, as far as I understand a constraint parameter, not variable at runtime.