DDR input without DPA in Arria II GX

Friends,

fyi, I got rid of fitter errors with the help of following posts

http://www.altera.com/support/kdb/solutions/rd07142008_32.html

http://www.altera.com/support/examples/functionality/pll-clocking-stratix3.html

- How would I "defparam" these dpa_divide_by and dpa_multiply_by when I dynamically configure my PLL through scan chain control; I do not know what entry in configuration .mif file corresponds to these parameter?

- I am never getting rx_dpa_locked asserted in my simulations, any idea why?

Regards,

Friends,

I am trying to use the dpa with external PLL but I am getting the fitter warning and error

DPA clock of SERDES receiver atom "rx_0" is driven by PLL "PLL_NAME" with unspecified dpa_multiply_by and dpa_divide_by parameters

Error: The lvds clock and the DPA clock frequency of SERDES receiver atom "rx_0" must be the same

The following support for interfacing DPA to external PLL does not apply because I do not see the option of "Use these clock settings for dpa clock" in PLL/lvds generated for Arria II GX

http://www.altera.com/support/kdb/solutions/rd11212007_95.html

Thanks in advance for your help!

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Can I use "rx_dpll_enable" at run time to dynamcially enable/diable dpa circuitry?

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Unlike Arria I, Arria II GX hasn't a DPA bypass multiplexer. It can be configured either in non-DPA or DPA mode at compile time. As with Arria I, you can however freeze the current DPA phase by asserting rx_dpll_hold. This is necessary, when the DPA adjustment is done based on a train pattern, but the regular bitstream isn't guaranteed to have edges.

The PLL actually produces the 8 phases of clock. All the altlvds instance w/DPA does is select which one to use for sampling the input data.

Jake

Friends,

I have instantiated an external PLL whose output clocks drive an alt_lvds instance which has dpa enabled. I am slightly confused about the operation of this circuit; is the dpa going to generate 8 phases from its input clock (output of external PLL) and choose the best one? On top of dpa ckt generating its own 8 phases, I can also adjust the phase of PLL output clock by varying PLL settings?

Can I use "rx_dpll_enable" at run time to dynamcially enable/diable dpa circuitry? "rx_dpll_enable" is mentioned in Arria literature but not in Arria II GX literature.

Thanks for your guidance!

I used it in virtex iv .. here is an instantiation

IDELAY # (

.IOBDELAY_TYPE ("VARIABLE"),

.IOBDELAY_VALUE (`DQ_DEFAULT_DLY)

)

IDLY_inst_[`data_width-1:0]

(

.O (idly_out[`data_width-1:0]),

.I (DDR_DQ[`data_width-1:0]), //ADC Data

.C (CLK),

.CE (dq_idelay_ce[`data_width-1:0]),

.INC (dq_idelay_inc[`data_width-1:0]),

.RST (dq_idelay_rst[`data_width-1:0])

);

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The lvds inputs can easily swictch at 1 GHz .. so arria ii gx can be used to communicate with 1G device ..

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1 GBPS LVDS is possible in DPA mode (because the DPA circuit is using it's own clock network), 945 GBPS in non-DPA mode, with fastest speed grade respectively So if you utilize DPA for your design, you can operate a SERDES at 1 GBPS, otherwise you can't (at least not by guaranteed specification). As said, DPA basically involves an automatic adjustment of receiver phase to the incoming data edges, but not setting a particular receiver phase manually.

In my opinion, several promising suggestions have been made. You should start trying the different options.

Regarding VCO lock range, I verified, that the about 1:2 range can be actually utilized with Cylone devices, it should also work with Arria II, that has a similar PLL specification. For a larger frequency range, dynamic reconfiguration would be necessary.

P.S.: Can you tell which XILINX devices have a runtime programmable IOBDELAY?

Hello

IDELAY does allow delay settings at runtime; I have used it myself.

According to the Arria II datasheet, the PLL input frequency is 5-500 MHz .. the memories can goto upto 390 MHz .. The lvds inputs can easily swictch at 1 GHz .. so arria ii gx can be used to communicate with 1G device ..

The only thing to figure out is what is the best way to do it (with the ability to adjust skew between ddr data and clock at run time) ..

All suggestions are welcome

My comment on IOBDELAY wasn't related to your describing words. My point is, that it's apparently not programmable at runtime, so it wouldn't help for your application, I think. The same with programmable IO delay provided by some Altera chips.

The timing resolution of PLL dynamic phase shift is basically one VCO ring oscillator stage delay. The same granularity is in effect for DPA, if I understand it right. Because the VCO operating range is 600 ... 1300 MHz, the delay increment could be 125 ps at 1000 MHz VCO frequency. It's generally preserved when dividing the clock.

std_logic is right however that 500 MHz frequency isn't feasible for internal or external clocks with Arria II. You would have to run two 90° phase shifted 250 MHz clocks with two DDR receivers in parallel.

P.S.: There's another point I just came upon. I have taken as granted, that PLLs have a limited lock range around the specified center frequency. Looking at the parameters supplied in PLL reconfiguration, there's obviously no frequency related parameter except charge pump current, that sets the PLL loop gain. So it can be expected, that the VCO should be able to lock within it's full specified frequency range. Thus with suitable divider parameters, a 1:2 lock range would be possible.

Arria II does have dynamically configurable PLLs.

I'm not sure you could 500MHz through Arria II IO however?? Have you checked timing in Quartus? I'd be interested in knowing what the top speed is.