DDR input without DPA in Arria II GX

Friends,

I have instantiated an external PLL whose output clocks drive an alt_lvds instance which has dpa enabled. I am slightly confused about the operation of this circuit; is the dpa going to generate 8 phases from its input clock (output of external PLL) and choose the best one? On top of dpa ckt generating its own 8 phases, I can also adjust the phase of PLL output clock by varying PLL settings?

Can I use "rx_dpll_enable" at run time to dynamcially enable/diable dpa circuitry? "rx_dpll_enable" is mentioned in Arria literature but not in Arria II GX literature.

Thanks for your guidance!