DDR input without DPA in Arria II GX

My comment on IOBDELAY wasn't related to your describing words. My point is, that it's apparently not programmable at runtime, so it wouldn't help for your application, I think. The same with programmable IO delay provided by some Altera chips.

The timing resolution of PLL dynamic phase shift is basically one VCO ring oscillator stage delay. The same granularity is in effect for DPA, if I understand it right. Because the VCO operating range is 600 ... 1300 MHz, the delay increment could be 125 ps at 1000 MHz VCO frequency. It's generally preserved when dividing the clock.

std_logic is right however that 500 MHz frequency isn't feasible for internal or external clocks with Arria II. You would have to run two 90° phase shifted 250 MHz clocks with two DDR receivers in parallel.

P.S.: There's another point I just came upon. I have taken as granted, that PLLs have a limited lock range around the specified center frequency. Looking at the parameters supplied in PLL reconfiguration, there's obviously no frequency related parameter except charge pump current, that sets the PLL loop gain. So it can be expected, that the VCO should be able to lock within it's full specified frequency range. Thus with suitable divider parameters, a 1:2 lock range would be possible.