New ContributorDDIO Output Timing Errors on a Source Synchronous Interface (RGMII)
Hi Intel Community,
I've got problems with the timing of a RGMII Interface.
In my design the FPGA imitates an Ethernet PHY. So the FPGA has to delay the RX and TX clock by 90 degree internally.
The FPGA is the Arria10: "10AX027H4F343SG" and I'm using Quartus Pro 21.2.
The RX Path is working without any timing errors, but the TX Path doesn't.
I've worked through:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an477.pdf
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an433.pdf
The clocking structure is like Figure 15. of an433 with clock_out delayed by 90°.
As PLL Compensation mode I tried "Source Synchronous" and "Normal", both have nearly the same result.
My SDC File:
# Generate 125 MHz Clock create_generated_clock -name RGMII125_TxClk -source [get_pins {inst_Rgmii1Slave|i_rgmiiPins|inst_rxPll|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|refclk[0]}] [get_pins {inst_Rgmii1Slave|i_rgmiiPins|inst_rxPll|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|outclk[1]}] # Apply a generated clock to the clk_out port create_generated_clock -name RGMII1Data_TxClk -source [get_pins {inst_Rgmii1Slave|i_rgmiiPins|inst_rxPll|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|outclk[2]}] [get_ports {pol_rgmii1_txClk}] derive_clock_uncertainty set t(maxDelay) 1.0 set t(minDelay) -1.0 # Set output delay based on the requirements mentioned previously set_output_delay -clock RGMII1Data_TxClk -max $t(maxDelay) [get_ports pov_rgmii1*] -add_delay set_output_delay -clock RGMII1Data_TxClk -min $t(minDelay) [get_ports pov_rgmii1*] -add_delay set_output_delay -clock RGMII1Data_TxClk -clock_fall -max $t(maxDelay) [get_ports pov_rgmii1*] -add_delay set_output_delay -clock RGMII1Data_TxClk -clock_fall -min $t(minDelay) [get_ports pov_rgmii1*] -add_delay set_output_delay -clock RGMII1Data_TxClk -max $t(maxDelay) [get_ports {pol_rgmii1_txCtl}] -add_delay set_output_delay -clock RGMII1Data_TxClk -min $t(minDelay) [get_ports {pol_rgmii1_txCtl}] -add_delay set_output_delay -clock RGMII1Data_TxClk -clock_fall -max $t(maxDelay) [get_ports {pol_rgmii1_txCtl}] -add_delay set_output_delay -clock RGMII1Data_TxClk -clock_fall -min $t(minDelay) [get_ports {pol_rgmii1_txCtl}] -add_delay # Set false paths to remove irrelevant setup and hold analysis set_false_path -fall_from [get_clocks RGMII125_TxClk] -rise_to [get_clocks RGMII1Data_TxClk] -setup set_false_path -rise_from [get_clocks RGMII125_TxClk] -fall_to [get_clocks RGMII1Data_TxClk] -setup set_false_path -fall_from [get_clocks RGMII125_TxClk] -fall_to [get_clocks RGMII1Data_TxClk] -hold set_false_path -rise_from [get_clocks RGMII125_TxClk] -rise_to [get_clocks RGMII1Data_TxClk] -hold set_false_path -to [get_ports {pol_rgmii1_txClk}]
The timing analysis looks like it takes the correct edges. But the timing is not so good...
Setup Violation:
Setup Waveform:
Hold Violation:
Hold Waveform:
Because setup and hold is violated I think I can't fix it with moving some edges. I have to improve something else in the design.
When I have a look in the "Resource Property View" I see that Quartus uses some weird DDIO component. Not the one that is included in the IO:
So I thought I can move it with the assignment:
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to pov_rgmii*
or
set_instance_assignment -name FAST_OUTPUT_REGISTER_REGISTER ON -to pov_rgmii1_tx[0] -entity top
But Quartus just ignores it:
The IO-Standard is 1.8-V HSTL Class II and the Slew Rate is set to 1.
I'm out of ideas.... Maybe the FPGA isn't fast enough? But it's just 125 MHz with 8 ns Period and a valid window of 2 ns per data.
That can't be so hard. What am I doing wrong?
Thanks a lot for your help!
Best regards,
Michael
